Integrated circuits can be connected to an external communication line, or bus, and traditionally include an output buffer, or driver circuit. An output buffer is typically characterized by a delay time experienced from applying a clock signal to an input of the buffer until valid data is provided at an output. This delay time is often referred to as Tco (time from clock to output). The performance of an integrated circuit/data line communication system is limited (among other things) by the variation in Tco. In general, if Tco is too long then the system operating frequency is reduced to allow time for the driven output to arrive at and set up a receiver connected to a remote end of the communication bus. If the delay is too short, the output may arrive at the receiver too quickly. Thus, variations in Tco need to be controlled to remain between the two limits imposed by the system and its design targets.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for an output buffer and circuitry which allows the output buffer delay time to be dynamically controlled.